Constitute a classification according to the internal circuits, pure analog chips, such as power management chip; pure digital chips, such as digital signal processing chip; mixed-signal chips. Mixed with the design of the chip design process described as an example, if there is wrong with this site go to the forum to criticize advice:
Mixed-chip digital chips to achieve some of the main functions of analog circuits serving the function of the realization of the digital circuit. At this stage most of the digital circuit chips are synchronous digital circuit, the hand of a small number of asynchronous digital circuit chip is not on this article. Digital circuits for the analog signal to rely on two areas: digital circuit at the clock, and the other is the external analog and digital circuits in the world interface. To achieve a specific way, is a phase locked loop (PLL) with high-quality crystal clock; according to the external interface input and output interfaces interface for ADC, DAC two major categories, namely, ADC, DAC. In addition to the module are two types of service module of simulation, such as the reference voltage source, voltage stability of the modules, such as oscillators. Often said that the analog circuit design most engineers focus on the two types of modular design. Traditional analog circuit design is in accordance with the requirements of the definition of specifications, has been selected for a mature industry module, in combination form to meet the specifications of the circuit, simulation software, such as HSPICE, SPECTER into the circuit simulation, verification indicators, If the specifications are met, is referred to the back-end designers. Chinese mainland at this stage simulated module innovative small, innovative small structure. As a result, analog circuit designers a hard effort is to Shubei mature types of circuit modules, when required to call directly, not blindly seek novelty odd. Road map to the back-end designers to draw a good map, available parasitic extraction tool to extract map published in the parasitic resistance and capacitance (no inductors), the resistance capacitance extraction directly to the formation of SPICE format text file, and the node LVS The original schematic node, and, RC this text file in the HSPICE direct input INCLUDE file in, HPICE to run again, and so on, that is, the completion of the so-called "post-simulation." After the simulation after passing the territory of production can be delivered. Number of hours full-custom circuit hardware description language and the realization of the two approaches. Custom-wide door is directly set up the basic circuit, which tends to be used in small-scale chip, you can save space and optimize performance, is the shortcomings of the long, difficult and error prone. HDL or VHDL is VerilogHDL for behavioral description of the function (Verilog description of the data flow, the description of the behavior, structure, description of the three methods described), prepared by the use of Verilog test vectors using Verilog simulation software (such as Verilog-xl) for the function Simulation. Simulation qualified, that function correctly. The next step is to function in the right document for the physical realization of HDL. Verilog to, for example. Class acts described in Verilog is no way to the realization of the direct physical. Physics will be achieved through behavioral description of the basic functions of the gate structures out. Verilog description of the structure of the transistor to support primitive level, gate-level primitive, Module of the original language Instantiation three structured description of the way, the only way to describe the structure of the Verilog in order to correspond with the gate, known as the gate-level Structured described in Verilog, usually referred to as gate-level Verilog. To describe the behavior (behavioral can register transfer level RTL, architecture level, the algorithm of the three-level class, class act in the general level to achieve RTL) into the Verilog description of the structure (gate) of the Verilog process, called " Comprehensive "(Synthesis), an integrated tool called Design Compile. Integrated gate-level Verilog after the automatic layout of the cloth to engineer automatic placement and routing, to generate the map. Digital and analog integration of the territory (which can be customized in the whole territory of the tool, can automatically place and route tools to carry out) with full-chip physical verification, production and delivery.